P 8.6-1 The input to the circuit shown in Figure P 8.6-1 is the voltage of the voltage source, v_s(t). The output is the voltage across the capacitor, v_o(t). Determine the output of this circuit when the input is v_s(t) = 8 – 15 u(t) V.

Figure P 8.6-1

So when t < 0, the power supply is providing 8 V and when t > 0, it is providing -7 V. So at steady state before t = 0, the fully charged capacitor is acting like an open circuit and we have

And after t = 0, and the circuit has reached steady state we again have the capacitor fully charged and acting like an open circuit with

So we know

And

Thevenin resistance is just the 6 Ω resistor, so using standard form and plugging in.

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